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8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
Ready/Busy# (RY/BY#)
The devices include a Ready/Busy# (RY/BY#) output signal. RY/BY# is an open drain output pin that
indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain out-
put, it allows several devices to be tied in parallel to V DD via an external pull-up resistor. After the rising
edge of the final WE# pulse in the command sequence, the RY/BY# status is valid.
When RY/BY# is actively pulled low, it indicates that an Erase or Program operation is in progress.
When RY/BY# is high (Ready), the devices may be read or left in standby mode.
Data# Polling (DQ 7 )
When the SST39VF801C/802C and SST39LF801C/802C are in the internal Program operation, any
attempt to read DQ 7 will produce the complement of the true data. Once the Program operation is
completed, DQ 7 will produce true data. Note that even though DQ 7 may have valid data immediately follow-
ing the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on
the entire data bus will appear in subsequent successive Read cycles after an interval of 1 μs. During internal
Erase operation, any attempt to read DQ 7 will produce a ‘0’. Once the internal Erase operation is com-
pleted, DQ 7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#)
pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the ris-
ing edge of sixth WE# (or CE#) pulse. See Figure 9 for Data# Polling timing diagram and Figure 23 for
a flowchart.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any consecutive attempts to read DQ 6 will produce
alternating ‘1’s and ‘0’s, i.e., toggling between 1 and 0. When the internal Program or Erase operation
is completed, the DQ 6 bit will stop toggling. The device is then ready for the next operation. For Sector-
, Block-, or Chip-Erase, the toggle bit (DQ 6 ) is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ 6 will be set to ‘1’ if a Read operation is attempted on an Erase-Suspended Sector/Block. If Pro-
gram operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ 6 will toggle.
An additional Toggle Bit is available on DQ 2 , which can be used in conjunction with DQ 6 to check
whether a particular sector is being actively erased or erase-suspended. Table 3 shows detailed status
bits information. The Toggle Bit (DQ 2 ) is valid after the rising edge of the last WE# (or CE#) pulse of
Write operation. See Figure 10 for Toggle Bit timing diagram and Figure 23 for a flowchart.
Table 3: Write Operation Status
Status
DQ 7
DQ 6
DQ 2
RY/BY#
Normal Operation
Erase-Suspend
Standard Program
Standard Erase
Read from Erase-Sus-
DQ 7 #
0
1
Toggle
Toggle
1
No Toggle
Toggle
Toggle
0
0
1
Mode
pended Sector/Block
Read from Non-Erase-
Data
Data
Data
1
Suspended Sector/Block
Program
DQ 7 #
Toggle
N/A
0
T3.0 25041
Note: DQ 7 and DQ 2 require a valid address when reading status information.
?2011 Silicon Storage Technology, Inc.
9
DS25041A
05/11
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